1. Field of the Invention
The present invention relates to a structure and a manufacturing method of manufacturing an AND-type non-volatile semiconductor memory device.
2. Description of the Background Art
A cross sectional structure of a memory cell in an AND-type flash memory which is an example of a conventional AND-type non-volatile semiconductor memory device is shown in FIG. 14. As shown in FIG. 14, a memory cell includes a source 3 and a drain 2, a floating gate 4, a control gate (word line) 5, and an insulating film 11. Source 3 and drain 2 are formed spaced apart on the main surface of a silicon substrate 1. On each side of these a field oxide film 6 is formed, and below the field oxide film 6 a channel stopper 18 is formed.
On the surfaces of source 3 and drain 2, an oxide film 17 is formed by thermally oxidizing of these surfaces.
A floating gate 4 includes a lower floating gate 4b and an upper floating gate 4a. Lower floating gate 4b is formed on the main surface of silicon substrate 1 with a tunnel oxide film 8 therebetween. On a side surface of lower floating gate 4b, a nitride film 15 and an oxide film sidewall 16 are formed. Nitride film 15 is provided to prevent a bird's beak from forming when oxide film 17 is formed.
Upper floating gate 4a extends over lower floating gate 4b and oxide film 17. Consequently, the coupling ratio between floating gate 4 and control gate 5 can be made relatively large, that is, approximately 0.6. On the other hand, the coupling ratio between floating gate 4 and silicon substrate 1 may be kept relatively small, since the area of the base of lower floating gate 4b is made small.
The inventor has independently discovered the following problems inherent in the above-mentioned conventional AND-type flash memory. These problems will be described in relation to FIG. 15 which is an enlarged view of a region 19 in FIG. 14.
It is difficult to prevent the formation of a bird's beak of oxide film 17 completely even if nitride film 15 is formed on a side surface of lower floating gate 4b, and a bird's beak 17a forms as shown in FIG. 15. Since the length of this bird's beak 17a may vary, the coupling ratio between silicon substrate 1 and floating gate 4 may also vary. In addition, due to the formation of bird's beak 17a, the thickness of tunnel oxide film 8 at each end may vary. Consequently, the erase and program characteristics effected by FN (Fowler-Nordheim) tunneling may vary as well.
Moreover, because the Vth distribution during the program/erase operations expands as a result, it is difficult to detect the narrow band Vth by introducing the multivalued technique. The multivalued technique enables one cell to hold a multi-bit data, and which distinguishes the cell states, typically distinguished between only two states using one reference voltage, into more than two states using a plurality of reference voltages.
Further, because of the presence of bird's beak 17a, it is possible that the regions where source/drain regions 3, 2 and the ends of floating gate 4 overlap and where the electrons pass during the program/erase operations may not be large enough. Thus, the ends of source 3 and drain 2 need to extend farther inward toward floating gate 4 than bird's beak 17a. Consequently, the number of thermal diffusion steps increases during the process flow, giving rise to the problem of higher production cost.
Moreover, hydrogen ions and holes are often trapped in nitride film 15 formed on a sidewall of lower floating gate 4b. These hydrogen ions and holes may undesirably couple with the electrons in floating gate 4, causing the electrons in floating gate 4 to be lost. In other words, retention, or the charge-holding characteristic of floating gate 4 into which the electrons are injected, may deteriorate, causing another problem. In addition, the movement of hydrogen ions and holes from nitride film 15 may degrade endurance.
Furthermore, as shown in FIG. 14 and FIG. 15, steps exist on the upper surface of oxide film 17. Specifically, large steps are formed near oxide film sidewall 16 and near field oxide film 6. Consequently, etch residues may be generated in the steps while upper floating gate 4a and control gate 5 are being patterned. In addition, the steps on the surface of oxide film 17 cause a side surface of a developed resist to have a wavelike shape, and the shapes of upper floating gate 4a and control gate 5 may vary. In such a case, adverse effects, especially on the erase characteristic, are to be expected.